F18A Architecture
18-bit stack-based core: registers, memory map, stacks, and extended arithmetic mode.
hardwareF18A Instruction Set
Complete opcode reference with slot encoding, instruction packing, and execution details.
hardwareNode Map
8×18 mesh topology, node numbering, and inter-node communication ports.
hardwareI/O System
Port addresses, GPIO pins, analog I/O, and the I/O register map.
hardwareBoot Process
Boot sequences, wire protocol, async boot streams, and multi-node loading.
hardwareApplication Notes
AN001–AN012: partner nodes, wire protocol, SPI flash, I2C, and more.
hardwarearrayForth Compiler
Compiler internals: tokenization, instruction packing, labels, directives, and ROM layout.
toolingProgramming Patterns
Idiomatic F18A patterns: loops, conditionals, inter-node messaging, and stack techniques.
patternscubec CLI
Command-line compiler for CUBE programs: options, JSON output, and disassembly.
toolingSample Programs
Catalog of CUBE and arrayForth samples with difficulty and behavior notes.
samples